Memory transistor array utilizing insulated word lines as gate electrodes

ABSTRACT

A semiconductor device enabling word lines to be arranged at close intervals, comprising a plurality of memory transistors arranged in an array and a plurality of word lines serving also as gate electrodes of memory transistors in a same row, extending in a row direction, and repeating in a column direction, where insulating films are formed between the plurality of word lines to insulate and isolate the word lines from each other and where a dimension of separation of word lines is defined by the thickness of the insulating films.

This is a continuation of application Ser. No. 10/196,636, filed Jul.17, 2002 now U.S. Pat. No. 6,891,262, the entire contents of which arehereby incorporated by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device having aplurality of interconnect lines arranged in parallel with each other,for example, word lines of a memory cell array, and a method ofproducing a semiconductor device shortening the distance betweeninterconnect lines to the maximum extent.

2. Description of the Related Art

The word lines of for example a flash electrically erasable andprogrammable read only memory (flash EEPROM) or other nonvolatile memorydevice serve also as gate electrodes of the memory transistors and arearranged extending in a row direction of the memory cell array. Theseword lines are repeatedly arranged at predetermined intervals in thecolumn direction. When bit lines are formed by patterning a metal,polycrystalline silicon, etc., the bit lines are also arranged inparallel to each other at predetermined intervals.

As other interconnect lines arranged in this way, there are word linesor bit lines of other memories (other read only memories (ROMs) orrandom access memories (RAMs)), gate lines of gate arrays, and numerousother interconnect lines.

When patterning such interconnect lines, first a conductive material isformed, then a resist is coated on the conductive material and patternson a reticle or other photomask are transferred to the resist. Using theresist to which the patterns have been transferred as a mask, theconductive material is then etched and patterned.

Alternatively, a material with a stronger resistance to etching isinterposed between the conductive material and resist, then the patternsof the resist are transferred once to the layer of the material with thestrong etching resistance. Next, the layer of the material with thestrong etching resistance to which the patterns are transferred is usedas a mask to etch and pattern the conductive material.

Summarizing the problems to be solved by the invention, with thesemethods, it is not possible to pattern the material at under theresolution limit of photolithography, which is dependent on thewavelength of the light used.

As a method for patterning a material at under the resolution limit ofphotolithography, the so-called “phase shift method” is known.

There is however a limit to the reduction of the distance betweeninterconnect lines by this method. It is not possible to reduce thedistance between interconnect lines to an extreme extent.

Therefore, in semiconductor memories of the related art, for example,the general practice has been to form the word lines in parallel stripesspaced apart from each other by the same extent as the widths as theword lines. This wasted space in the column direction and has been onefactor obstructing the reduction of the bit cost.

The problem of the limit to reduction of area due to the interconnectline pitch is basically found in all semiconductor devices with numerousfine repeating interconnect line patterns such as other interconnectlines of the memory devices and interconnect lines of gate arrays.

SUMMARY OF THE INVENTION

A first object of the present invention is to provide a semiconductordevice including a plurality of interconnect lines of isolatedstructures enabling arrangement at a much closer distance than in thepast.

A second object of the present invention is to provide a method ofproducing a semiconductor device enabling formation of a plurality ofinterconnect lines at a much closer distance than in the past whileisolating them from each other.

To attain the first object, according to a first aspect of the presentinvention, there is provided a semiconductor device comprising aplurality of memory transistors arranged in an array, a plurality ofword lines serving also as gate electrodes of memory transistors in asame row, arranged extending in a row direction, and repeating atdistances in a column direction, and an insulating film being formedbetween the word lines so that the word lines are insulated and isolatedfrom each other, the device wherein a dimension of the distance betweenword lines is defined by a thickness of the insulating film.

To attain the first object, according to a second aspect of the presentinvention, there is provided a semiconductor device having a pluralityof interconnect lines arranged in parallel with each other and havingadjoining interconnect lines isolated by an insulator, wherein aninsulator between the interconnect lines comprises a sidewall insulatinglayer formed at one side surface of two adjoining interconnect lines andhaving an approximately ¼ circular sectional shape.

To attain the first object, according to a third aspect of the presentinvention, there is provided a semiconductor device having a pluralityof interconnect lines arranged in parallel with each other and havingadjoining interconnect lines isolated by an insulator, wherein theinsulator between the interconnect lines, comprises a sidewallinsulating layer formed at one side surface of two adjoininginterconnect lines and having an approximately ¼ circular sectionalshape, and an insulating film formed between the sidewall insulatinglayer and the interconnect line and having a dimension in the directionof separation of the sidewall insulating layer and the interconnect linedefined by the film thickness.

In the semiconductor devices of the first to third aspects of theinvention, a plurality of interconnect lines (hereinafter including wordlines) are arranged extending in one direction in parallel. Here,“arranged extending in one direction” does not require that theinterconnect lines be necessarily straight. It also includes the casewhere they for example wind toward the same direction.

The interconnect lines are isolated by insulators. In the first aspectof the invention, adjoining interconnect lines are isolated by aninsulating film interposed so that the distance between the interconnectlines becomes the film thickness. In the second aspect of the invention,adjoining interconnect lines are isolated by a sidewall insulating layerformed at one side surface of the adjoining interconnect lines. In thethird aspect of the invention, adjoining interconnect lines are isolatedby a sidewall insulating layer and insulating film interposed betweenthe sidewall insulating layer and one interconnect line so that thedistance between them becomes the film thickness.

In these semiconductor devices, since the distance between interconnectlines is determined by the thickness of the insulating film and/or widthof the sidewall insulating layer, the distance between interconnectlines is much smaller than the width of the interconnect lines. As theinsulating film, it is possible to use a charge storage film having acharge storage capability provided in the memory transistor extending onthe sidewall and top surface of every other interconnect line.

To attain the second object, according to a fourth aspect of theinvention, there is provided a method of producing a semiconductordevice comprising a plurality of memory transistors arranged in an arrayand a plurality of word lines serving also as gate electrodes of memorytransistors in a same row, arranged extending in a row direction, andrepeating in a column direction, an insulating film being formed betweenthe word lines so that the word lines are insulated and isolated fromeach other, a dimension of the distance between word lines being definedby a thickness of said insulating film, the method of producing asemiconductor device comprising the steps of forming stacked patterns offirst charge storage films comprised of a plurality of films and havinga charge storage capability and first word lines on a semiconductor inparallel with each other at predetermined distances, forming a secondcharge storage film comprised of a plurality of films and having acharge storage capability on surfaces of said first word lines and onsemiconductor regions exposed between said first word lines, and formingbetween said first word lines second word lines having at least partsburied between said first word lines where a second charge storage filminterposed.

To attain the second object, according to a fifth aspect of theinvention, there is provided a method of producing a semiconductordevice comprising a plurality of interconnect lines arranged in parallelwith each other and having two adjoining interconnect lines isolated byan insulator, comprising the steps of forming a plurality of sacrificiallayers in parallel with each other at predetermined intervals, formingsidewall insulating layers of approximately ¼ circular sectional shapesat the two side surfaces of the sacrificial layers, removing thesacrificial layers, depositing a conductive film so as to bury thespaces between the sidewall insulating layers, and grinding theconductive film from the surface so as to form a plurality ofinterconnect lines isolated by the sidewall insulating layers.

To attain the second object, according to a sixth aspect of theinvention, there is provided a method of producing a semiconductordevice comprising a plurality of interconnect lines arranged in parallelwith each other and having two adjoining interconnect lines isolated byan insulator, comprising the steps of forming a plurality of firstinterconnect lines in parallel with each other at predeterminedintervals, forming sidewall insulating layers at the two side surfacesof the first interconnect lines, depositing a conductive film so as tobury the spaces between the sidewall insulating layers, and grinding theconductive film from the surface so as to form a plurality of secondinterconnect lines isolated from the first interconnect lines by thesidewall insulating layers between the first interconnect lines.

The methods of production of a semiconductor device according to thefifth and sixth aspects of the invention are for the semiconductordevice according to the second aspect of the invention.

To attain the second object, according to a seventh aspect of theinvention, there is provided a method of producing a semiconductordevice comprising a plurality of memory transistors arranged on asemiconductor in an array and a plurality of word lines serving also asgate electrodes of memory transistors in a same row, extending in a rowdirection, and repeating in a column direction, two adjoining word linesbeing isolated by a sidewall insulating layer formed at a side surfaceof one word line and having an approximately ¼ circular sectional shapeand an insulating film formed on a surface of the sidewall insulatinglayer, the method comprising the steps of forming a plurality ofsacrificial layers in parallel with each other at predeterminedintervals on the semiconductor, forming sidewall insulating layers ontwo side surfaces of the sacrificial layers, removing the sacrificiallayers, forming a charge storage film including charge storage meansinside on the surfaces of the sidewall insulating layers and on regionsof the semiconductor exposed between the sidewall insulating layers,depositing a conductive film so as to bury recesses in the surface ofthe charge storage film, and grinding the conductive film from thesurface to form a plurality of word lines isolated by the sidewallinsulating layers and the charge storage film.

This method of production is for the semiconductor device of the thirdaspect of the invention. The insulating film between word lines is madethe charge storage film rather than a thermal oxide film.

To attain the second object, according to an eighth aspect of theinvention, there is provided a method of producing a semiconductordevice comprising a plurality of memory transistors arranged on asemiconductor in an array and a plurality of word lines serving also asgate electrodes of memory transistors in a same row, extending in a rowdirection, and repeating in a column direction, two adjoining word linesbeing isolated by a sidewall insulating layer formed at a side surfaceof one word line and having an approximately ¼ circular sectional shapeand an insulating film formed on a surface of the sidewall insulatinglayer, the method comprising the steps of forming a plurality ofmultilayer films, each comprising a charge storage film including chargestorage means inside and a first conductive film, on the semiconductorin parallel with each other at predetermined intervals, forming sidewallinsulating layers on two side surfaces of the multilayer films, againforming a charge storage film including charge storage means inside onthe surfaces of the sidewall insulating layers and on regions of thesemiconductor exposed between the sidewall insulating layers, depositinga second conductive film so as to bury recesses in the surface of thecharge storage film, and grinding the second conductive film from thesurface to form a plurality of word lines isolated by the sidewallinsulating layers and the charge storage film.

This method of production is for the semiconductor device of the thirdaspect of the invention. The insulating film between the word lines ismade the charge storage film. Further, a thermal oxide film may beformed.

To attain the second object, according to a ninth aspect of theinvention, there is provided a method of producing a semiconductordevice comprising a plurality of memory transistors arranged on asemiconductor in an array and a plurality of word lines serving also asgate electrodes of memory transistors in a same row, extending in a rowdirection, and repeating in a column direction, two adjoining word linesbeing isolated by a sidewall insulating layer formed at a side surfaceof one word line and having an approximately ¼ circular sectional shapeand an insulating film formed on a surface of the sidewall insulatinglayer, the method comprising the steps of forming a charge storage filmincluding charge storage means inside on the semiconductor, forming aplurality of conductive layers comprising first conductive films inparallel with each other at predetermined intervals on the chargestorage film, forming sidewall insulating layers on two side surfaces ofa plurality of conductive layers, removing portions of the chargestorage film between the sidewall insulating layers by etching using theconductive layers and the sidewall insulating layers as masks, againforming a charge storage film including charge storage means inside onthe surfaces of the conductive layers, on the surfaces of the sidewallinsulating layers, and on regions of the semiconductor exposed betweenthe sidewall insulating layers, depositing a second conductive film soas to bury recesses in the surface of the charge storage film formedagain, and grinding the second conductive film from the surface to forma plurality of word lines isolated by the sidewall insulating layers andthe charge storage film.

This method of production is for the semiconductor device of the thirdaspect of the invention. The insulating film between word lines is madethe charge storage film. Further, a thermal oxide film may be formed. Inthe ninth aspect of the invention, etching damage is harder to occur atthe semiconductor surface at the time of processing the conductive layerand sidewalls compared with the method of producing of the eighth aspectof the invention.

In the methods of production of a semiconductor device according to thefourth to ninth aspects of the invention explained above, a high densityword line arrangement is realized by just repeating two times anoperation of stacking and patterning a charge storage film and word linematerial.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other objects and features of the present invention willbecome clearer from the following description of the preferredembodiments given with reference to the attached drawings, wherein:

FIGS. 1A to 1C are a plan view and sectional views of the configurationof a semiconductor memory device having a virtual ground type memorycell array according to a first embodiment of the present invention;

FIGS. 2A and 2B are sectional views of the state after formation offirst word lines in the production of the semiconductor memory deviceaccording to the first embodiment;

FIG. 3 is a sectional view of the state when etching a substrate in theproduction of the semiconductor memory device according to the firstembodiment;

FIG. 4 is a sectional view of the state after forming a second chargestorage film in the production of the semiconductor memory deviceaccording to the first embodiment;

FIG. 5 is a sectional view of the state after formation of a resistpattern for a processing mask of second word lines in the production ofthe semiconductor memory device according to the first embodiment;

FIG. 6 is a plan view of the configuration of a semiconductor memorydevice having a NAND type memory cell array according to a secondembodiment of the present invention;

FIGS. 7A and 7B are a sectional view and enlarged view of theconfiguration of a semiconductor memory device having a NAND type memorycell array according to the second embodiment of the present invention;

FIGS. 8A and 8B are sectional views of the state after formation offirst word lines in the production of the semiconductor memory deviceaccording to the second embodiment;

FIG. 9 is a sectional view of the state when etching a substrate in theproduction of the semiconductor memory device according to the secondembodiment;

FIG. 10 is a sectional view of the state after formation of a secondcharge storage film in the production of the semiconductor memory deviceaccording to the second embodiment;

FIG. 11 is a sectional view of the state after formation of a resistpattern for a processing mask for second word lines in the production ofthe semiconductor memory device according to the second embodiment;

FIG. 12 is a graph of the results of measurement when investigatingvariations in thickness of a thermal oxide film due to rapid thermalnitridation so as to explain the need for etching the substrate in theproduction of the semiconductor memory device according to the first andsecond embodiments of the present invention;

FIG. 13 is a sectional view of the state after patterning the first wordlines in the production of a nonvolatile memory device according to athird embodiment;

FIG. 14 is a sectional view of the state after formation of a thermaloxide film in the production of the nonvolatile memory device accordingto the third embodiment;

FIG. 15 is a sectional view of the state after formation of a thermaloxide film in the production of the nonvolatile memory device accordingto the third embodiment;

FIGS. 16A and 16B are a sectional view and plan view showing theproblems in the first to third embodiments to be solved in theproduction of a nonvolatile memory device according to a fourthembodiment of the present invention;

FIG. 17 is a plan view of a pattern of word lines around a memory cellarray of the nonvolatile memory device according to the fourthembodiment;

FIG. 18 is a plan view of the pattern of word lines of a nonvolatilememory device showing locations of removal of residue in a first methodof preventing leakage according to a fifth embodiment of the presentinvention;

FIG. 19 is a sectional view of a nonvolatile memory device along theline A—A of FIG. 18 and shows the state after removal of residue usingthe first method of preventing leakage according to the fifthembodiment;

FIG. 20 is a plan view of the pattern of word lines of a nonvolatilememory device in the case of using a second method of preventing leakageaccording to the fifth embodiment;

FIG. 21 is a view of the configuration of a nonvolatile memory deviceusing a third method of preventing leakage according to the fifthembodiment;

FIGS. 22A and 22B are a plan view and a sectional view along the lineA—A showing the interconnect line structure of a semiconductor deviceaccording to a sixth embodiment of the present invention;

FIGS. 23A and 23B are a plan view and a sectional view along the lineA—A of the state after formation of a sacrificial layer in theproduction of the semiconductor device according to the sixthembodiment;

FIG. 24 is a sectional view of the state after deposition of adielectric in the production of the semiconductor device according tothe sixth embodiment;

FIGS. 25A and 25B are a plan view and sectional view along the line A—Aof the state after formation of sidewalls in the production of thesemiconductor device according to the sixth embodiment;

FIGS. 26A and 26B is a plan view and sectional view along the line A—Aof the state after removal of a sacrificial layer in the production ofthe semiconductor device according to the sixth embodiment;

FIG. 27 is a sectional view of the state after deposition of aconductive film in the production of the semiconductor device accordingto the sixth embodiment;

FIG. 28 is a sectional view of the state after formation of first shapeinterconnect lines in the production of a semiconductor device accordingto a seventh embodiment of the present invention;

FIG. 29 is a sectional view of the state after formation of a thermaloxide film in the production of the semiconductor device according tothe seventh embodiment;

FIG. 30 is a sectional view of the state after deposition of adielectric in the production of the semiconductor device according tothe seventh embodiment;

FIG. 31 is a sectional view of the state after formation of sidewalls inthe production of the semiconductor device according to the seventhembodiment;

FIG. 32 is a sectional view of the state after deposition of aconductive film in the production of the semiconductor device accordingto the seventh embodiment;

FIG. 33 is a sectional view of the interconnect line structure of thesemiconductor device according to the seventh embodiment;

FIGS. 34A to 34C are a plan view and sectional views along the line A—Aand line B—B of a NOR type memory cell array according to an eighthembodiment of the present invention;

FIGS. 35A and 35B are a plan view and a sectional view along the lineA—A of the state after formation of a sacrificial layer in theproduction of the semiconductor device according to the eighthembodiment;

FIG. 36 is a sectional view of the state after deposition of adielectric in the production of the semiconductor device according tothe eighth embodiment;

FIGS. 37A and 37B are a plan view and a sectional view along the lineA—A of the state after formation of the sidewalls in the production ofthe semiconductor device according to the eighth embodiment;

FIGS. 38A and 38B are a plan view and a sectional view along the lineA—A of the state after removal of the sacrificial layer in theproduction of the semiconductor device according to the eighthembodiment;

FIG. 39 is a sectional view of the state after deposition of aconductive film in the production of the semiconductor device accordingto the eighth embodiment;

FIG. 40 is a plan view of a NAND type memory cell array according to aninth embodiment of the present invention;

FIGS. 41A and 41B are a sectional view along the line A—A of the NANDtype memory cell array according to the ninth embodiment and a partiallyenlarged view of the same;

FIGS. 42A and 42B are a plan view and a sectional view along the lineA—A of the state after formation of a sacrificial layer in theproduction of a semiconductor device according to the ninth embodiment;

FIG. 43 is a sectional view of the state after deposition of adielectric in the production of the semiconductor device according tothe ninth embodiment;

FIGS. 44A and 44B are a plan view and a sectional view along the lineA—A of the state after formation of sidewalls in the production of thesemiconductor device according to the ninth embodiment;

FIGS. 45A and 45B are a plan view and a sectional view along the lineA—A of the state after removal of a sacrificial layer in the productionof the semiconductor device according to the ninth embodiment;

FIG. 46 is a sectional view of the state after deposition of aconductive film in the production of the semiconductor device accordingto the ninth embodiment;

FIGS. 47A and 47B are a plan view and a sectional view along the lineA—A of the state after formation of word lines in the production of thesemiconductor device according to the ninth embodiment;

FIG. 48 is a sectional view of the state after processing selection gatelines in the production of the semiconductor device according to theninth embodiment;

FIGS. 49A and 49B are a plan view and a sectional view along the lineA—A of the state after formation of source-drain regions in theproduction of the semiconductor device according to the ninthembodiment;

FIGS. 50A to 50C are sectional views of the state up to deposition of adielectric in the production of a semiconductor device according to a10th embodiment of the present invention;

FIGS. 51A to 51D are sectional views of the state up to formation ofword lines in the production of the semiconductor device according tothe 10th embodiment;

FIGS. 52A to 52C are sectional views of the state up to deposition of adielectric in the production of a semiconductor device according to an11th embodiment of the present invention; and

FIGS. 53A to 53C are sectional views of the state up to formation ofword lines in the production of the semiconductor memory deviceaccording to the 11th embodiment.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Preferred embodiments of the present invention will be described indetail below while referring to the attached figures.

FIRST EMBODIMENT

The first embodiment relates to the first aspect of the presentinvention, that is, relates to a nonvolatile memory device having avirtual ground (VG) type memory cell array.

FIG. 1A is a plan view of a VG type memory cell array using the presentinvention to reduce the distance between word lines. Further, FIG. 1B isa sectional view along the line A—A of FIG. 1A, while FIG. 1C is asectional view along the line B—B of FIG. 1A.

As shown in FIG. 1C, the surface of a P-type semiconductor substrate SUBis formed with source-drain regions S/D comprising N-type impurityregions separated from each other. The source-drain regions S/D, asshown in FIG. 1A, form bit lines BL1, BL2, BL3, BL4 . . . and has apattern of lines extending in the column direction arranged in parallelstripes shown in a whole cell array.

The substrate regions sandwiched between the source-drain regions S/Dare called “channel formation regions”. These channel formation regionsend up forming parallel stripes extending in the column direction.

Word lines WL1, WL2, WL3, WL4, WL5 . . . are arranged extending in therow direction perpendicularly intersecting the channel formation regionsand source-drain regions S/D. As shown in FIG. 1B, the sectional shapesof the even numbered word lines WL2, WL4 . . . and odd numbered wordlines WL1, WL3, WL5 . . . differ somewhat. In the present embodiment,the even numbered word lines WL2, WL4 . . . are formed on thesemiconductor substrate SUB in the state with the charge storage filmGD1 interposed. In the present embodiment, the even numbered word linesbecome the “first word lines”. Further, the charge storage film GD1corresponds to the “first charge storage film” in the present invention.

A charge storage film GD2 is formed covering the surfaces of the firstword lines WL2, WL4 . . . and the surfaces of the substrate regionsexposed between the first word lines. Further, the odd numbered wordlines WL1, WL3, WL5 . . . are formed between the first word lines in thestate with the charge storage film GD2 interposed. In the presentembodiment, the odd numbered word lines WL1, WL3, WL5 . . . become the“second word lines”. The word lines as a whole comprise the second wordlines and the first word lines arranged alternately. Further, the chargestorage film GD2 corresponds to the “second charge storage film” in thepresent invention.

Explaining the relationship between the first and second word lines inmore detail, the bottom surfaces of the second word lines face thesemiconductor regions between the first word lines in the state with thecharge storage film GD2 interposed. Almost all portions of the sides ofthe second word lines face the sides of the first word lines in thestate with the charge storage film GD2 interposed. Further, the two endsof each of the second word lines in the width direction ride up over theends of the adjoining two first word lines in the width direction in thestate with the charge storage film GD2 interposed.

In this way, the word lines in the present embodiment are insulated andisolated by the interposed charge storage film GD2 so that the spacebetween each two adjoining word lines becomes the film thickness in theseparation direction. Note that the word lines are comprised of dopedpolycrystalline silicon or doped amorphous silicon.

In the present embodiment, MONOS type memory transistors are shown asexamples, so the charge storage films GD1 and GD2 are each so-called“ONO types” comprising three layers.

Specifically, each of the charge storage films GD1 and GD2 comprises abottommost layer of a first potential barrier film BTM, a middle layerof a charge trap film CHS, and a topmost layer of a second potentialbarrier film TOP. The first potential barrier film BTM comprises, forexample, a thermal-oxidized silicon film obtained by thermally oxidizingthe substrate surface to form a silicon oxide film or an oxynitride filmobtained by nitriding the thermal-oxidized silicon film. The charge trapfilm CHS comprises for example silicon nitride or silicon oxynitride andincludes a large number of charge traps inside it as dispersed chargestoring means. The second potential barrier film TOP is comprised of forexample a silicon oxide film.

Note that in the case of a so-called MNOS type, the second potentialbarrier film TOP is omitted, and the charge trap film CHS is formedrelatively thick. Further, in the case of a so-called nanocrystal type,innumerable microparticles comprised of for example polycrystallinesilicon are buried discretely between the first potential barrier filmand oxide film.

The potential barrier films GD1 and GD2 have a total thickness,converted to silicon dioxide, of about 10 odd nm.

The potential barrier films GD1 and GD2 are formed so that the filmstructure including the film thickness becomes equal in portionscontiguous with the monocrystalline silicon (semiconductor substrateSUB). The portions contiguous with the polycrystalline silicon oramorphous silicon of the potential barrier film GD2 (first word linesWL2, WL4 . . . ) however become thicker than the portions contiguouswith the monocrystalline silicon when converted to silicon dioxide. Thisis because the thermal oxidation rate of the polycrystalline silicon oramorphous silicon becomes about two times the thermal oxidation rate ofthe monocrystalline silicon. Therefore, the insulation characteristicsbetween the word lines are secured at a level not posing a problem.

At the time of writing data, when injecting charges into the storageportion 1 shown in FIG. 1C, a positive drain voltage is supplied to thebit line BL3 and a reference voltage to the bit line BL4, while apredetermined positive voltage is supplied to the word line WL2. At thistime, the electrons supplied from the source-drain region S/D formingthe bit line BL4 are accelerated in the channel, whereby a high energyis obtained at the bit line BL3 side. The potential barrier of the firstpotential barrier film BTM is exceeded, whereby the charge is injectedinto and stored at the storage portion 1.

When injecting a charge into the storage portion 2, the voltage isswitched between the bit lines BL3 and BL4. Due to this, the electrondonor side and the side where the electrons become “hot” energy wisebecome opposite to the above case, whereby the electrons are injectedinto the storage portion 2.

When reading data, a predetermined read drain voltage is suppliedbetween the bit lines BL3 and BL4 so that the storage portion where thebit data to be read was written becomes the source. Further, anoptimized positive voltage able to turn on the channel portionsandwiched between the storage portions of the two sides, but low enoughnot to change the threshold voltages of the storage portions at the twoends of the memory transistor is supplied to the word line WL2. At thistime, the conductivity of the channel is effectively changed due to theamount of charge stored in the storage portion to be read or thepresence or absence of a charge. As a result, the stored information isread out converted to an amount of current or a potential difference ofthe drain side.

When reading the other bit data, the bit line voltage is changed so thatthe storage portion where that bit data has been written becomes thesource, whereby the data is read out in the same way as above.

When erasing data, an erase voltage of a direction opposite to that atthe time of writing the data is supplied so that the channel formationregion and source-drain region S/D side becomes high and the word lineWL2 side becomes low. Due to this, the stored charge is drained from oneor both of the storage portions to the substrate SUB side, and thememory transistor returns to the erased state. Note that as anothererasing method, it is also possible to adopt the method of injectinginto the storage portion, by attracting it by the electric field of thecontrol gate, the high energy charge occurring at the source-drainregion S/D side or near a not shown PN junction inside of the substrate,having a polarity opposite to the stored charge, and caused byband-to-band tunneling.

The procedure for formation of a VG type memory cell array will beexplained next while referring to the drawings. This procedure forformation relates to the fourth aspect of the present invention.

FIGS. 2A and 2B to FIG. 5 are sectional views (and plan views) of stepsin the formation of word lines. FIG. 2A is a plan view, while FIG. 2B isa sectional view along the line A—A of FIG. 2A. FIG. 3. to FIG. 5 areall sectional views along the line A—A.

The semiconductor substrate SUB is formed with wells and injected withions for adjusting the threshold voltage in accordance with need.Further, a resist or other mask layer is formed on the semiconductorsubstrate and ions injected, then activate the substrate to formsource-drain regions S/D (bit lines BL1, BL2, BL3, BL4 . . . )

The semiconductor substrate SUB is formed with a first charge storagefilm for forming the charge storage film GD1. For example, the surfaceof the semiconductor substrate SUB is thermally oxidized to form thefirst potential barrier film BTM and the first potential barrier filmBTM is nitrided in accordance with need and form a charge trap film CHScomprised of silicon nitride or silicon oxynitride on the firstpotential barrier film BTM, then the surface of the charge trap film CHSis thermally oxidized or otherwise treated used to form the secondpotential barrier film TOP.

The first charge storage film GD1 has deposited on it a conductive filmcomprised of doped polycrystalline silicon or doped amorphous silicon byfor example chemical vapor deposition (CVD).

The conductive film is formed with a resist pattern, then isanistropically etched by reactive ion etching (RIE) etc. to pattern theconductive film. Next, the parts of the first charge storage filmexposed between the conductive film patterns are patterned by a dryetching system using for example CF₄/CHF₃/Ar. Next, the resist patternsare removed. Due to this, multilayer patterns comprising the chargestorage film GD1 and first word lines WL2 or WL4 are formed in parallelstripe patterns perpendicularly intersecting the source-drain regionsS/D as shown in FIG. 2A.

As shown in FIG. 3, the surface layer of the semiconductor substrate SUBis etched. This etching may be performed by ordinary dry etching, but amethod using sacrificial oxidation is preferable. That is, the surfaceof the substrate is thermally oxidized to form a thin sacrificial oxidefilm, then this is removed by wet etching etc. Due to this, the surfacelayer of silicon consumed at the time of sacrificial oxidation is etcheduniformly without leaving damage. The conditions for this sacrificialoxidation are determined in advance in accordance with the conditionsfor formation of the first charge storage film (charge storage film GD1)so that the nitrogen atoms introduced into the substrate surface layerare sufficiently removed.

As shown in FIG. 4, the second charge storage film is formed under thesame conditions as the first charge storage film. Due to this, thesecond charge storage film (charge storage film GD2) is formed.

As shown in FIG. 5, a conductive film WLF completely burying the firstword lines WL2, WL4, . . . , for example, a film of dopedpolycrystalline silicon or doped amorphous silicon, is deposited.

On this conductive film WLF are formed resist patterns R opening abovethe first word lines WL2, WL4, . . .

Next, the resist patterns R are used as a mask for RIE or otheranistropic etching. Due to this, the conductive film WLF is etched intoisolated sections and the second word lines WL1, WL3, WL5, . . . shownin FIG. 1B are formed.

SECOND EMBODIMENT

The second embodiment relates to the first aspect of the presentinvention and relates to a nonvolatile memory device having a NAND typememory cell array.

FIG. 6 is a plan view of a NAND type memory cell array using the presentinvention to reduce the distance between word lines. Further, FIG. 7A isa sectional view along the line A—A of FIG. 6, while FIG. 7B is asectional view enlarging part of FIG. 7A.

As shown in FIG. 7A and FIG. 7B, a P-type semiconductor substrate SUB isformed with word lines WL1, WL2, . . . WLn of substantially the samesectional structures as in the first embodiment. That is, the oddnumbered word lines WL1, WL3, . . . , WLn (first word lines) are formedon the semiconductor substrate SUB where a charge storage film GD1interposed. A charge storage film GD2 is formed covering the surfaces ofthe first word lines WL1, WL3, . . . . , WLn and the surfaces of thesubstrate regions exposed between the first word lines. Further, evennumbered word lines WL2, WL4, . . . (second word lines) are formedbetween the first word lines in the state with the charge storage filmGD2 interposed. More particularly, the bottom surfaces of the secondword lines face the semiconductor regions between the first word linesin the state with the charge storage film GD2 interposed. The main sidesof the second word lines face the sides of the adjoining first wordlines in the state with the charge storage film GD2 interposed. Further,the two ends of the second word lines in the width direction ride upover the ends of the adjoining two first word lines in the widthdirection in the state with the charge storage film GD2 interposed.

In this way, the word lines in the present embodiment are insulated andisolated by the interposed charge storage film GD2 so that the spacebetween each two adjoining word lines in the separation directionbecomes the film thickness. Note that the word lines are comprised ofdoped polycrystalline silicon or doped amorphous silicon.

The charge storage films GS1 and GD2 comprise, for example in the caseof a MONOS type memory transistor, a bottommost layer of a firstpotential barrier film BTM, a middle layer of a charge trap film CHS,and a topmost layer of a second potential barrier film TOP in the sameway as in the first embodiment.

At the outside of the word line WL1 a control gate line SG1 isolated byfor example the charge storage film GD2 is arranged in parallel.Similarly, at the outside of the word line WLn a control gate line SG2isolated by for example the charge storage film GD2 is arranged inparallel. These control gate lines SG1 and SG2 serve also as gateelectrodes of select transistors and are faced to the semiconductorsubstrate SUB with a gate isolation film GD3 interposed. The gateisolation film GD3 is comprised for example of a single layer of asilicon dioxide film. In this case, the production process becomessomewhat complicated, but the single layer of the gate isolation film isformed only at those portions and the select transistors become ordinaryMOS types. Alternatively, the charge storage films GD2 and gateisolation film GD3 are made the same films and a charge is preventedfrom being injected into the portions of the gate isolation film GD3 bythe applied bias conditions.

At the outside of the control gate line SG1 is formed a drain region DRcomprised of an N-type impurity region. This drain region DR is sharedwith a not shown other NAND string.

Further, at the outside of the control gate line SG2, a common sourceline CSL comprised of an N-type impurity region is formed. The commonsource line CSL is shared with one row's worth of the NAND string in therow direction and a not shown other row's worth of the NAND stringadjoining it in the column direction.

The transistors forming these NAND strings have formed on them aninterlayer insulating film INT. The interlayer insulating film INT hasbit lines BL1 and BL2 arranged on it in parallel stripes. The bit linesare connected to the corresponding drain regions DR by bit contacts BCformed at the interlayer insulating film INT.

When writing data, if injecting charges into the storage portion 1 shownin FIG. 7B, a positive drain voltage is supplied to the bit line BL2, areference voltage is supplied to the common source line CSL, and avoltage for turning on two select transistors is supplied to the controlgate lines SG1 and SG2. The word lines WL1, WL2, WL4 . . . WLn otherthan the word line WL3 to which the cell to be written on is connectedare supplied with a pass voltage enabling transmission of the abovedrain voltage or above reference voltage to the cell to be written on.Due to this, a predetermined write drain voltage is supplied between thesource and drain of the memory transistor forming the cell to be writtenin. In this state, a predetermined program voltage is supplied to theword line WL3. At this time, the electrons supplied from the source sideto the channel in FIG. 7B are accelerated in the channel, a high energyis obtained at the drain side end of the channel, the potential barrierof the first potential barrier film BTM is exceeded, and the charge isinjected and stored in the storage portion 1.

When injecting a charge in the storage portion 2, the voltage isswitched between the bit line BL2 and the common source line CSL. Due tothis, the electron supply side and the side where the electrons becomehot energy-wise become opposite to the above case and electrons areinjected into the storage portion 2.

As a still more preferable method of writing data, it is possible to usesource side injection. In this case, when writing data into the storageportion 1, a reference voltage is supplied to the bit line BL2, while adrain voltage is supplied from the common source line. Further, thevoltage supplied to the word line WL2 more close to the source by onefrom the word line WL3 to which the cell to be written on is connectedis not a simple pass voltage, but a voltage optimized to enable sourceside injection. Due to this, the lateral direction electric fieldbecomes strong near the boundary between the word line WL2 and word lineWL3 and electrons can be injected more efficiently to the source end(storage portion 1) of the memory transistor.

When injecting a charge in the storage portion 2, the voltage betweenthe bit line BL2 and the common source line CSL is switched and thevoltage of the word line 4 is optimized to a value enabling source sideinjection. Due to this, the electron supplying side and side where theelectrons become hot energy-wise become opposite to the above case andelectrons are injected into the storage portion 2.

When reading data, a predetermined read drain voltage is suppliedbetween the bit line BL2 and the common source line CSL so that thestorage portion where the bit to be read is written becomes the source,while a pass voltage is supplied to the word lines other than the wordto which the cell to be read is connected. Further, an optimizedpositive voltage able to turn on the channel portion sandwiched betweenthe storage portions of the two sides, but low enough not to change thethreshold voltages of the storage portions at the two ends of the memorytransistor is supplied to the word line WL3. At this time, theconductivity of the channel is effectively changed due to the amount ofcharge stored in the storage portion to be read or the presence orabsence of a charge. As a result, the stored information is read outconverted to an amount of current or a potential difference of the drainside.

When reading the other bit data, the voltage between the bit line BL2and the common source line CLS is changed so that the storage portionwhere that bit data has been written becomes the source, whereby thedata is read out in the same way as above.

When erasing data, either the charge is drained to the substrate sideusing FN tunneling over the entire channel or the charge is drained tothe word line side for block erasure.

The procedure for formation of a NAND type memory cell array will beexplained next while referring to the drawings. FIG. 8A is a plan view,while FIG. 8B is a sectional view along the line A—A of FIG. 8A. FIG. 9to FIG. 11 are all sectional views along the line A—A.

The semiconductor substrate SUB is formed with wells and injected withions for adjusting the threshold voltage in accordance with need.

The semiconductor substrate SUB is formed with a first charge storagefilm GD1. For example, the surface of the semiconductor substrate SUB isthermally oxidized to form the first potential barrier film BTM, thenthe first potential barrier film BTM is nitrided in accordance withneed, and form a charge trap film CHS comprised of silicon nitride orsilicon oxynitride on the first potential barrier film BTM, then thesurface of the charge trap film CHS is thermally oxidized or otherwisetreated used to form the second potential barrier film TOP.

The first charge storage film GD1 has deposited on it a conductive filmcomprised of doped polycrystalline silicon or doped amorphous silicon byfor example CVD.

The conductive film is formed with resist patterns, then isanistropically etched by RIE etc. to pattern the conductive film. Next,the parts of the first charge storage film exposed between theconductive film patterns are patterned by a dry etching system using forexample CF₄/CHF₃/Ar. Next, the resist patterns are removed. Due to this,multilayer patterns comprising the charge storage film GD1 and firstword lines WL1, WL3, . . . WLn are formed in parallel stripe patterns asshown in FIG. 8A.

As shown in FIG. 9, the surface layer of the semiconductor substrate SUBis etched. This etching may be performed by ordinary dry etching, but amethod using sacrificial oxidation is preferable. That is, the surfaceof the substrate is thermally oxidized to form a thin sacrificial oxidefilm, then this is removed by wet etching etc. Due to this, the surfacelayer of silicon consumed at the time of sacrificial oxidation is etcheduniformly without leaving damage. The conditions for this sacrificialoxidation are determined in advance in accordance with the conditionsfor formation of the first charge storage film GD1 so that the nitrogenatoms introduced into the substrate surface layer are sufficientlyremoved.

As shown in FIG. 10, the second charge storage film is formed under thesame conditions as the first charge storage film. Due to this, thesecond charge storage film GD2 is formed. In accordance with need, thecharge storage film GD2 of the region outward from the word line WL1 andthe region outward from the word line WLn is selectively removed toselectively form a single layer of an insulating film GD3 at thoseportions.

As shown in FIG. 11, a conductive film WLF completely burying the firstword lines WL1, WL3, . . . , WLn, for example, a film of dopedpolycrystalline silicon or doped amorphous silicon, is deposited.

On this conductive film WLF are formed resist patterns R opening abovethe first word lines WL1, WL3, . . . , WLn.

Next, the resist patterns R are used as a mask for RIE or otheranistropic etching. Due to this, the conductive film WLF is etched intoisolated sections and the second word lines WL2, WL4, . . . shown inFIG. 7B are formed.

The semiconductor substrate regions outward from the selection gatelines SG1 and SG2 are injected with ions of N-type impurities. At thistime, since the ions do not pass through the regions where the wordlines are arranged, source-drain regions are not formed.

Next, the interlayer insulating film INT is deposited, bit contacts BCare formed, and bit lines are formed to complete the NAND typenonvolatile memory device.

Note that in the above first embodiment and second embodiment, thesecond word lines to be formed later may be formed so as to bury thespaces between the first word lines and not overlap with the lines. Inthis case, it is preferable to form a stopper film for preventingchemical mechanical polishing (CMP) or other polishing on the first wordlines. Further, in a structure not allowing overlap, it is possible tooptimize the ion injection conditions in the NAND type so as to causethe ions to pass through the space between word lines (charge storagefilm GD2) and form narrow source-drain impurity regions S/D in the wordline direction.

In the semiconductor memory devices according to the above firstembodiment and second embodiment, since the distance between word linesis determined by the thickness of the multilayer film (charge storagefilm GD2), the distance between word lines is much smaller than thewidth of the word lines. Therefore, it is possible to realize 2F² (F:resolution limit of lithography or design rule) and a memory cell withan extremely small area as a cell for storing 2-bit data.

Further, with the method of producing a semiconductor memory deviceaccording to the above embodiments, a high density word line arrangementis realized just by repeating twice the operation of stacking a chargestorage film and word line material and patterning the same.

Further, since the substrate is etched thin before forming the secondcharge storage film, the precision of formation of the second chargestorage film is improved.

Here, the inventors prepared a wafer A processed by rapid thermalnitridation (RTN) when forming the first charge storage film and a waferB not processed by RTN and thermally oxidized them assuming formation ofthe first potential barrier film of the second charge storage film.

The table of FIG. 12 shows the measured values of the oxide film. Here,to accurately measure the film thickness, the surface was thermallyoxidized long with the aim of 18 nm. The thickness of the thermal oxidefilm was measured at five measurement points in the wafer.

As a result, it was learned that with thermal oxidation of the wafer Aprocessed by RTN, the oxidation rate is low and the variation in thethickness of the oxide film is larger than the wafer B. This is becausenitrogen is introduced into the substrate at the time of RTN and thisnitrogen obstructs the oxidation.

In the above embodiment of the present invention, before the formationof the second charge storage film, the surface of the substrate wasoxidized to form a sacrificial oxide film, then this oxide film wasetched to remove the nitrogen-containing surface layer of the substrate.Due to this, the second charge storage film can be formed with a goodprecision and variation of characteristics can be suppressed.

THIRD EMBODIMENT

The third embodiment relates to a partial change of the steps of thefirst and second embodiments.

At the step of FIG. 2B of the first embodiment or the step of FIG. 8B ofthe second embodiment explained above, the conductive film pattern andthe first charge storage film are continuously dry etched to formpatterns comprising the first charge storage film GD1 and first wordlines WL2 or WL4. With dry etching, however, the substrate is damagedsomewhat. This is therefore not that preferable.

Here, the method was considered of dry etching only the conductive filmpatterns and removing the first charge storage film for forming thefirst charge storage film GD1 by wet etching.

When the first charge storage film is an ONO film, there is siliconnitride. This cannot be removed by a silicon oxide etchant comprisedmainly of fluoric acid. Processing using hot phosphoric acid becomesnecessary. In processing by hot phosphoric acid, however, the newproblem arises of the high concentration polycrystalline silicon surfaceending up being etched.

The third embodiment provides a method of production suitable forremoving this first charge storage film by wet etching.

The method shown in this embodiment can be applied to all types, notonly the VG type or NAND type, so the explanation will be given hereusing FIG. 13 to FIG. 15 showing sections along the line A—A.

FIG. 13 is a sectional view at the time of patterning the conductivematerial on the ONO structure first charge storage film GD1 to form thefirst word lines WLi, WLi+2, . . . and corresponds to FIG. 2B and FIG.8B.

When the dry etching of the conductive material ends, parts of thesecond potential barrier film TOP are sometimes shaved off depending onthe amount of over etching. In some cases, as illustrated, the secondpotential barrier film TOP is removed around the first word lines.

In this embodiment, at this time, the surfaces of the first word linesWLi, WLi+2, . . . are thermally oxidized to form, as shown in FIG. 14, athermal oxide film TOX of about 10 nm on the surface of the first wordlines.

Further, the portions of the first charge storage film GD1 exposedbetween the first word lines are removed by wet etching in the statewith the surfaces of the first word lines protected by the thermal oxidefilm TOX. That is, the silicon nitride film (charge trap film CHS) isremoved by an etchant using hot phosphoric acid and the silicon dioxidefilm (first potential barrier film BTM) is removed by an etchant mainlycomprised of fluoric acid.

At the time of etching, naturally the thermal oxide film TOX alsobecomes thinner. In this embodiment, the thickness of the thermal oxidefilm TOX may also be set in advance so that the thermal oxide film isetched off at the time of the end of this etching. Alternatively, asshown in FIG. 15, the film may be made thicker to a certain extent sothat the thermal oxide film TOX remains.

Whatever the case, there is the advantage that the amount of the firstword lines shaved off is reduced compared with the case where thethermal oxide film is not formed.

Next, in the same way as the first and second embodiments, the secondcharge storage film GD2 is formed, the spaces between the first wordlines are buried with a conductive material, then this is patterned toform the second word lines WLi−1, WLi+1, . . .

Note that when leaving the thermal oxide film TOX to the end, theinsulation characteristics between the word lines are remarkablyimproved at the thermal oxide film and the parasitic capacitance betweenthe word lines is also reduced.

FOURTH EMBODIMENT

The fourth embodiment is a modification of the first to thirdembodiments. More specifically, it relates to patterns of electrodetakeout parts and addition of some steps for preventing short-circuitsbetween electrodes.

In the step of FIG. 5 of the first embodiment explained above or thestep of FIG. 11 of the second embodiment pattern the second word lines.In the etching at that time, since the underlying layer is the secondcharge storage film GD2, it is not possible to set too excessive an overetching time. The reason is that if the second charge storage film GD2becomes thin at this portion due to excessive over etching, theinsulation characteristics between word lines are liable to deteriorate.

After the etching of the second word lines, conductive residue of thematerial of the second word lines sometimes is left near the outskirtsof the first word lines as shown for example in FIG. 16A. In particular,when depositing the conductive layer for forming the second word lines(for example, polycrystalline silicon), if this becomes thinner than theother regions at the regions above the first word lines, residue of theconductive material is liable to remain at the outskirts of the firstword lines.

This residue is formed along the end surfaces of the first word lines asshown in FIG. 16B and ends up short-circuiting second word lines.

In the present embodiment, a step is added for cutting the residuemidway so as to prevent short-circuits between word lines.

Further, if the word lines are formed by a pitch close to the minimumline width of photolithography as in the first to third embodiments, itbecomes difficult to take out electrodes for connecting the word linesto the upper interconnect lines. In the present embodiment, mention willalso be made of details of patterns for facilitating takeout ofelectrodes.

FIG. 17 shows patterns of ends including electrode takeout parts of wordlines in this embodiment.

The arrangement of word lines in the memory cell array is the same as inthe first or second embodiments.

The word lines extending from the memory cell array to one direction arebent in a direction different from the direction of arrangement. Here,they are bent 90 degrees in the column direction from the row direction.The locations where the word lines are bent are successively shifted.The pitch of the locations of the word lines extending in the columndirection is eased from the pitch in the memory cell array. Therefore,room is given for formation of broad electrode takeout parts PAD1 andPAD2 for connecting the word lines to not shown upper interconnectlines. The first word lines WL1 a, WL1 b, and WL1 c formed from thefirst layer polycrystalline silicon have electrode takeout parts PAD1,while the second word lines WL2 a, WL2 b, and WL2 c formed from thesecond layer polycrystalline silicon and partially overlapping the firstword lines at the two sides have electrode takeout parts PAD2. Amongthese, the electrode takeout parts PAD1 are arranged at positionsfurther outward from the electrode takeout parts PAD2.

At the other ends of the word lines as well, the first word lines WL1 a,WL1 b, and WL1 c extend further outward fro the second word lines WL2 a,WL2 b, and WL2 c.

The reason for extending the first word lines outward is to remove theconductive residue remaining at the peripheries of the first word linesat the ends of the first word lines to prevent the second word linesfrom electrically short-circuiting at the time of formation of thesecond word lines.

Specifically, at the time of the step of FIGS. 2A and 2B of the firstembodiment, the step of FIGS. 8A and 8B of the second embodiment, orformation of the first word line in the FIG. 13 to FIG. 15 of the thirdembodiment, as shown in FIG. 17, a photomask of patterns of first wordlines with one ends formed relatively long, with electrode takeout partsPAD1 formed at the front ends, and with other ends formed relativelylong is used.

The steps of FIG. 3 and FIG. 4 or FIG. 9 and FIG. 10 are then followedto form the second charge storage film GD2, then the step of FIG. 5 orFIG. 11 is used to deposit polycrystalline silicon for forming thesecond word lines and resist patterns R are formed over it. At thistime, as shown in FIG. 17, a photomask of patterns of second word lineswith one ends formed relatively short (that is, shorter than the firstword lines), with electrode takeout parts PAD2 formed at the front ends,and with other ends formed shorter than the first word lines is used.

Next, in the present embodiment, a step for removing the conductiveresidue is added. For example, resist patterns with openings made at thebroken line parts A1 and A2 shown in FIG. 17 to expose the ends of thefirst word lines and covering and protecting the second word lines as awhole are formed. The resist patterns are used as a mask for partialover etching. The conditions of the etching gas etc. at this time aremade the same as the time of the formation of the second word lines. Theetching time is made the time by which the conductive residue issufficiently removed at the openings. Due to this, the conductiveresidue is cut at those portions and the second word lines arecompletely electrically isolated.

Next, the same steps as in the first or second embodiment are followedto complete the nonvolatile memory.

FIFTH EMBODIMENT

The present embodiment is for solving other problems due to residue ofthe second word line forming material.

Under the residue shown in FIG. 16A, the second charge storage film GD2remains in a complete form protected by the residue and maintaining thecharge storage capability in the high state. As opposed to this, thesecond charge storage film GD2 of the surroundings is removed or even ifremaining is exposed to etching, so falls considerably in charge storagecapability.

The charge storage film under the residue sometimes stores a chargeduring gate processing or operation. In the case where the cells areN-channel types, the storage of electrons raises the threshold voltage,so there is not that much of a problem, but if holes are stored, thechannels directly under the residue become depletion channels and theleakage between the sources and drains of the cells increases. Further,even if not a depletion type, if the threshold voltage is low, due tothe capacitive coupling with the adjoining word lines to which the highpositive voltage has been supplied, the potential of the residue in theelectrically floating state rises, the channels of the parasitictransistors turn on, and the leakage increases.

The increase in the leakage gives rise to the disadvantages ofparticularly reducing the S/N ratio of the read signal for all cells atthe time of reading and in turn causing mistaken reading.

This embodiment is for prevent such an increase in leakage. In thepresent embodiment, there are the following three methods of preventingleakage.

The first method selectively removes the residue at those portions.

The second method prevents the occurrence of residue at those portionsby providing an odd number of word lines.

The third method takes into consideration the fact that the number ofword lines is usually an even number and, in addition to the secondmethod, uses the outside word line as a dedicated line for supplying aleakage prevention voltage.

Next, these three methods will be successively explained with referenceto the drawings. Note that the drawings used here also use thetechnology of the above fourth embodiment overlappingly, but thisoverlapping application is not necessarily essential. Further, thecomponents assigned reference numerals already explained will not beexplained overlappingly here.

FIG. 18 is a plan view of a location of removal of residue in the firstmethod. Further, FIG. 19 is a sectional view along the line A—A of FIG.18 after removal of residue using the first method.

In the resist patterns R for removing the residue of the second wordlines used in the fourth embodiment, in addition to the openings A1 andA2, as shown in FIG. 18, an opening A3 opening at least near the longside of the one of the outermost side first word lines, here, the wordline WL1 a, is added in advance on the patterns. Therefore, at the timeof etching using the resist patterns R as a mask, the residue of theconductive material forming the second word lines exposed from theopening A3 as shown in FIG. 19 in addition to the openings A1 and A1 iseffectively removed.

As a result, according to the first method, the advantage is obtainedthat the leakage current caused by the residue in the opening A3 isprevented or reduced.

FIG. 20 is a plan view of the case of use of the second method.

In the second method, an odd number of word lines is provided. That is,if the number of the first word lines is “n”, (n+1) second word linesare provided. Due to this, second word lines are arranged at theoutermost positions of the memory cell array. As a result, the problemof leakage due to residue of the second word lines is resolved.

Note that the usual number of word lines is even. Compared with this,one extra word line is added. In this case, it is also possible toconfigure the device so that for example an address signal is notallocated to the extra word line so as not to use it.

FIG. 21 gives a plan view and block diagram of the case of use of thethird method.

In this third method, in the same way as in the second method, thenumber of word lines is made an odd number. Among these, the n number ofword lines WL1 a to WL2 c have connected to them an ordinary word linedrive circuit 51 driven by a row decoder 50 for decoding an input rowaddress signal RAD. On the other hand, the extra one second word lineWL2 is not driven by the row decoder 50 and is supplied with a writevoltage at all times regardless of the write data. Further, a word linedrive circuit 52 is connected for supplying a predetermined voltage forturning off the channel at all times at the time of a read operation.This word line drive circuit 52 corresponds to the “first word linedrive circuit” in the present invention, while the ordinary word linedrive circuit 51 driven by the row decoder 50 corresponds to the “secondword line drive circuit” in the present invention.

In this third method, by optimizing the voltage supplied by the wordline drive circuit 52, the channel directly under the word line WL2 iskept in the off state at all times and leakage current is prevented atthe time of a read operation. Alternatively, by maintaining the writeoperation at all times regardless of the write data, electrons aresufficiently stored at all times in the charge storage film GD2 directlyunder the word line WL2. By making all of the cells using the word lineWL2 gate enhancement types, occurrence of leakage current is prevented.

SIXTH EMBODIMENT

This embodiment relates to a semiconductor device according to thesecond aspect of the present invention.

FIG. 22A is a plan view of the state after formation of interconnectlines of a semiconductor device according to the sixth embodiment, whileFIG. 22B is a sectional view along line A—A of FIG. 22A.

This semiconductor device uses the interconnect line isolation structureof the present invention for the plurality of interconnect linesarranged in parallel at one layer.

A dielectric 1 supported on a substrate SUB is formed with first shapeinterconnect lines IL1 having substantially vertical sides or forwardtapered sectional shapes. Further, between the first shape interconnectlines IL1 are formed second shape interconnect lines IL2 having at leasttop portions with reverse tapered sectional shapes. The first shapeinterconnect lines IL1 and second shape interconnect lines IL2 haveinterposed between them sidewall insulating layers having approximately¼ circular sectional shapes (hereinafter simply called “sidewalls”) SW.Due to this, two adjoining interconnect lines are insulated andisolated. Here, the “approximately ¼ circular sectional shape” means ashape having a first side of an approximately flat shape and a secondside including at least a curved surface curved to an arc so as tobecome closer to the first side the higher up such as shown in FIG. 22B.

The sidewalls SW are formed at the sides of the first shape interconnectlines IL1. Therefore, the surfaces of the sidewalls SW opposite to thefirst shape interconnect lines IL1 are curved. The second shapeinterconnect lines IL2 are formed so as to be buried in recesses formedin the curved surfaces. As a result, the second shape interconnect linesIL2 have reverse tapered sectional shapes.

Note that the first and second shape interconnect lines IL1 and IL2 needonly be parallel with each other. For example, they may also be windingas a whole. Further, they may be interconnect lines directly contactingthe substrate SUB (for example, Schottkey metal).

Next, the procedure for formation of the interconnect lines will beexplained while referring to the drawings. This procedure for formationrelates to the fifth aspect of the present invention.

FIGS. 23A and 23B to FIG. 27 are sectional views (and plan views) ofsteps in the formation of interconnect lines. FIG. 23A, FIG. 25A, andFIG. 26A are plan views, while FIG. 23B, FIG. 25B, and FIG. 26B aresectional views along the line A—A. The other figures are all sectionalviews along the line A—A.

As shown in FIGS. 23A and 23B, a dielectric 1 on a substrate SUB isformed with a plurality of sacrificial layers 2 comprised ofdielectrics. The plurality of sacrificial layers 2 are formed in stripesparallel to each other at pitches of about two times the interconnectlines to be formed.

As shown in FIG. 24, an insulating film 3 of a different material isdeposited so as to cover the sacrificial layers 2. The material of theinsulating film 3 selected is a material with a high etching selectivityto the sacrificial layers 2. For example, the sacrificial layers 2 aremade silicon nitride films, while the insulating film 3 is made asilicon dioxide film. Further, parts of the insulating film 3 remain asthe sidewalls in the end, so the material and method of formation areselected in consideration of the quality and insulation characteristicsof the film.

Next, the insulating film 3 is etched back by anistropic etching. Due tothis, as shown in FIGS. 25A and 25B, sidewalls SW are formed at thesides of the sacrificial layers 2. The widths of the sidewalls SW aremainly determined by the height of the sacrificial layers 2 and theconditions of the anistropic etching. When the anistropy is strong to acertain extent, however, even if the etching time varies somewhat, thewidths of the sidewalls do not change much, so the uniformity isrelatively high.

Next, the sacrificial layers 2 are selectively removed by apredetermined method. For example, with removal in the case where thesacrificial layers 2 are silicon nitride, wet processing using anetchant including fluoric acid FH is performed. Due to this, sidewallsSW remain as shown in FIG. 26A and FIG. 26B.

As shown in FIG. 27, a conductive film 4 completely burying thesidewalls SW, for example, a film of a metal, doped polycrystallinesilicon, or doped amorphous silicon, is deposited.

Next, for example, CMP or another method is used to grind and/or polishthe surface of the conductive film 4. The grinding and/or polishing iscontinued until the sidewalls SW are exposed, the conductive film 4isolated into a plurality of regions, and the isolation distance becomesthe necessary value. Due to this, a plurality of interconnect lines IL1and IL2 isolated by the sidewalls SW are formed at the necessarydistances.

In the sixth embodiment, the distance between interconnect lines isdetermined by the sidewall insulating layers SW, so it is possible toreduce the distance between interconnect lines sufficiently from thelimit of photolithography. At this time, the controllability of thedistance between interconnect lines is also high.

SEVENTH EMBODIMENT

The seventh embodiment relates to a semiconductor device according tothe third aspect of the present invention.

FIG. 33 is a sectional view of the interconnect line structure accordingto the third aspect.

The plan view of this interconnect line structure is similar to FIG.22A. The interconnect line structure comprises a plurality ofinterconnect lines IL1 and IL2 arranged in parallel stripes. In thesectional view, the alternate arrangement of the first shapeinterconnect lines IL1 and the second shape interconnect lines 2 itselfis common with FIG. 22B.

In the interconnect line isolation structure in the seventh embodiment,not only the sidewalls SW, but also the interposition of the thinthermal oxide film 10 between the sidewalls SW and the first shapeinterconnect lines IL1 differ from the first embodiment.

The thermal oxide film 10 is obtained by thermally oxidizing the surfaceof the first shape interconnect lines IL1 when they are dopedpolycrystalline silicon or doped amorphous silicon. Therefore, thecontrollability of the film thickness is extremely high. Further, thefilm is silicon dioxide obtained by thermal oxidation, so the quality isgood. Therefore, there is the advantage that the insulationcharacteristics between interconnect lines are improved.

FIG. 28 to FIG. 32 are sectional views in the formation of theinterconnect line structure.

As shown in FIG. 28, a dielectric 1 supported on a substrate SUB isformed with first shape interconnect lines IL1 at a pitch of about twotimes the final interconnect lines. The first shape interconnect linesIL1 are finally left, so are formed from doped polycrystalline siliconor doped amorphous silicon.

As shown in FIG. 29, the surfaces of the first shape interconnect linesIL1 are thermally oxidized to form thermal oxide films 10 comprised ofseveral nm to several tens of nm of silicon dioxide. Note that insteadof thermal oxidation, it is also possible to nitride or oxynitride thesurfaces by heating.

Next, in the same way as the seventh embodiment, an insulating film 3 isdeposited (FIG. 30). This is etched to form sidewalls SW (FIG. 31).Further, a conductive film 4 is deposited (FIG. 32), and this is groundand/or polished to form the plurality of interconnect lines IL1 and IL2.

In the seventh embodiment, it is possible to effectively improve theinsulation characteristics by just thermal oxidation or otherprocessing. Note that the step of removing the sacrificial layers as inthe first embodiment is unnecessary. Therefore, there is no increase inthe number of steps.

EIGHTH EMBODIMENT

The eighth embodiment shows a first example of the case of applicationof the method of formation of interconnect lines of the sixth embodimentto formation of word lines of a nonvolatile memory. Here, application toa NOR type memory cell array will be explained.

FIG. 34A is a plan view of a NOR type memory cell array using thepresent invention to reduce the distance between word lines. Further,FIG. 34B is a sectional view along the line A—A of FIG. 34A, while FIG.34C is a sectional view along the line B—B of FIG. 34A.

As shown in FIG. 34C, a P-type semiconductor substrate SUB is formedwith source-drain regions S/D comprised of N-type impurity regionsseparated from each other. The source-drain regions S/D, as shown inFIG. 34A, form source lines SL1, SL2, . . . and bit lines BL1, BL2, . .. and have patterns of lines long in the column direction arranged inparallel stripes in the cell array as a whole.

The sidewalls SW are formed on the semiconductor substrate SUB extendinglong in a direction perpendicular to the source-drain regions S/D and inparallel.

A charge storage film GD is formed covering the surfaces of thesidewalls SW and the surface of the semiconductor substrate SUB. Thecharge storage film GD is a film including charge storing means inside.In the present embodiment, MONOS type memory transistors areillustrated, so the charge storage film GD comprises three layers offilms of a so-called ONO type.

Specifically, the charge storage film GD comprises a bottommost layer ofa first potential barrier film BMT, a middle layer of a charge trap filmCHS, and a topmost layer of a second potential barrier film TOP. Thefirst potential barrier film BTM comprises a thermal-oxidized siliconfilm obtained for example by thermally oxidizing the substrate surfaceto form a thermal silicon oxide film or an oxynitride film formed bynitriding the thermal-oxidized silicon film. The charge trap film CHS iscomprised for example of silicon nitride or silicon oxynitride andincludes in it a large number of charge traps as dispersed chargestoring means. The second potential barrier film TOP is comprised forexample of a silicon oxide film.

Note that in the case of a so-called MONOS type, the second potentialbarrier film TOP is omitted and the charge trap film CHS is formedrelatively thickly. Further, in floating gate (FG) type using aconductive layer as the charge storage film, often the first potentialbarrier film and floating gate are stacked from the bottom and aninter-gate insulating film comprised of an ONO film is stacked on top ofthem.

The charge storage film GD has a total thickness of 10 odd nm or soconverted to silicon dioxide. A conductive material is buried inrecesses in the surface of the charge storage film GD. Due to this,wordlines WL1, WL2, . . . , W5, are formed. In the illustrated example,the even numbered word lines WL2, WL4, . . . have first shapes, whilethe odd numbered word lines WL1, WL3, . . . have second shapes.

Next, the procedure for formation of this NOR type memory cell arraywill be explained with reference to the drawings.

FIGS. 35A and 35B to FIG. 39 are sectional views (and plan views) ofsteps in the formation of word lines. FIG. 35A, FIG. 37A, and FIG. 38Aare plan views, while FIG. 35B, FIG. 37B, and FIG. 38B are sectionalviews along the line A—A. The other figures are all sectional viewsalong the line A—A.

First, the semiconductor substrate SUB is if necessary provided with alayer for isolating elements by a dielectric and injected with ions foradjusting the threshold voltage. A resist or other mask layer is formedon the semiconductor substrate and injected with ions, then activate itto form source-drain regions S/D (source lines SL1 and SL2 and bit linesBL1 and BL2).

As shown in FIG. 35A, a plurality of sacrificial layers 20 comprised ofdielectrics are formed on the substrate SUB in parallel stripe patternsperpendicular to the source-drain regions S/D. The plurality ofsacrificial layers 20 are formed in stripe shapes parallel with eachother at pitches of about two times that of the word lines to be formed.

As shown in FIG. 36, an insulating film 3 of a different material isdeposited so as to cover the sacrificial layers 20. The material of theinsulating film 3 selected is a material with a high etching selectivitywith respect to the sacrificial layers 20. For example, the sacrificiallayers 20 are made silicon nitride films, while the insulating film 3 ismade a silicon dioxide film. Further, parts of the insulating film 3remain in the end as the sidewalls, so the material and method offormation are selected in consideration of the quality and insulationcharacteristics etc. of the film.

Next, the insulating film 3 is etched back by anistropic etching. Due tothis, as shown in FIG. 37A and FIG. 37B, sidewalls SW are formed at thesides of the sacrificial layers 20. The widths of the sidewalls SW aremainly determined by the height of the sacrificial layers 20 and theconditions of the anistropic etching. When the anistropy is strong to acertain extent, however, even if the etching time varies somewhat, thewidths of the sidewalls do not change much, so the uniformity isrelatively high.

Next, the sacrificial layers 20 are selectively removed by apredetermined method. For example, with removal in the case where thesacrificial layers 20 are silicon nitride, wet processing using anetching including phosphoric acid (H₃PO₄) is performed. Due to this,sidewalls SW remain as shown in FIG. 38A and FIG. 38B.

As shown in FIG. 39, a conductive film 4 completely burying thesidewalls SW, for example, a film of a metal, doped polycrystallinesilicon, or doped amorphous silicon, is deposited.

Next, for example, CMP or another method is used to grind and/or polishthe surface of the conductive film 4. The grinding and/or polishing iscontinued until the sidewalls SW are exposed, the conductive film 4isolated into a plurality of regions, and the isolation distance becomesthe necessary value. Due to this, a plurality of word lines WL1, WL2, .. . WL5, isolated by the sidewalls SW are formed at the necessarydistances.

Note that the grinding and/or polishing is continued until the chargetrap film CHS is completely separated for each word line. In the case ofan FG type where the charge storage film is a conductive material,however, separation of the charge storage film becomes essential. Thisis because if a floating gate FG is connected at such a location, thestored charge would leak to the adjoining cell and therefore datastorage itself would become impossible. Further, sufficient grindingand/or polishing is necessary to avoid concentration of the electricfield at that portion.

NINTH EMBODIMENT

The ninth embodiment shows a second example of the case of applicationof the method of formation of interconnect lines of the sixth embodimentto formation of word lines of a nonvolatile memory. Here, application toa NAND type memory cell array will be explained.

FIG. 40 is a plan view of a NAND type memory cell array using thepresent invention to reduce the distance between word lines. Further,FIG. 41A is a sectional view along the line A—A of FIG. 40, while FIG.41B is a sectional view enlarging part of FIG. 41A.

As shown in FIG. 41A and FIG. 41B, a P-type semiconductor substrate SUBis formed with word lines WL1, WL2, . . . WLn of substantially the samesectional structures as in the sixth embodiment. That is, thesemiconductor substrate SUB is formed with sidewalls SW in the form ofparallel stripes. A charge storage film GD is formed covering thesurface of the sidewalls SW and the semiconductor substrate SUB. Forexample, in a MONOS type memory transistor, in the same way as in thesixth embodiment, the charge storage film GD comprises a bottommostlayer of a first potential barrier film BMT, a middle layer of a chargetrap film CHS, and a topmost layer of a second potential barrier filmTOP.

This charge storage film GD has a total thickness of 10 odd nm or soconverted to silicon dioxide. A conductive material is buried inrecesses in the surface of the charge storage film GD whereby word linesWL1, WL2, . . . , WLn are formed. In the illustrated example, the oddnumbered word lines WL1, WL3, . . . have first shapes, while the evennumbered word lines WL2, WL4, . . . have second shapes.

At the outside of the word line WL1, a control gate line SG1 isolated bythe sidewalls SW is arranged in parallel. Similarly, at the outside ofthe word line WLn, a control gate line SG2 isolated by the sidewalls SWis arranged in parallel. These control gate lines SG1 and SG2 are facedto the semiconductor substrate SUB where a charge storage film GDinterposed in FIG. 41A, but no charge is injected into the chargestorage film GD of those portions due to the applied bias conditions.Note that the production process becomes somewhat complicated, but thesingle layer of the charge storage film is formed only at those portionsand the select transistors may be made ordinary MOS types.

With this interconnect line structure, source-drain regions S/Dcomprised of N-type impurity regions are formed only at the substrateportions around the regions below the sidewalls SW. The source-drainregions S/D are formed discretely only between word lines or a word lineand control gate line. The lateral direction in FIG. 40 is isolated bynot shown element isolation layers (for example, LOCOS).

A drain region DR comprised of an N-type impurity region is formedoutside of the control gate film SG1. This drain region DR is sharedwith a not shown other NAND string.

Further, a common source line CSL comprised of an N-type impurity regionis formed outward from the control gate SG2. The common source line CSLis shared inside one row's worth of a NAND string arranged in the rowdirection and with a not shown other row's worth of the NAND stringadjoining it in the column direction.

The transistors forming these NAND strings have formed on them aninterlayer insulating film INT. The interlayer insulating film INT hasbit lines BL1, BL2 arranged on it in a parallel stripe form. The bitlines are connected with the corresponding drain regions DR by bitcontacts BC formed on the interlayer insulating film INT.

Next, the procedure for formation of this NAND type memory cell arraywill be explained with reference to the drawings.

FIGS. 42A and 42B to FIGS. 49A and 49B are sectional views (and planviews) of steps in the formation of word lines. FIG. 42A, FIG. 44A, FIG.45A, FIG. 47A, and FIG. 49A are plan views, while FIG. 42B, FIG. 44B,FIG. 45B, FIG. 47B, and FIG. 49B are sectional views along the line A—A.The other figures are all sectional views along the line A—A.

First, the semiconductor substrate SUB is if necessary provided with anelement isolation layer and injected with ions for adjusting thethreshold voltage.

As shown in FIG. 42A, a plurality of sacrificial layers 30 comprised ofdielectrics are formed on the substrate SUB in parallel stripe patterns.The plurality of sacrificial layers 30 are formed in stripe shapesparallel with each other at pitches of about two times that of the wordlines to be formed.

As shown in FIG. 43, an insulating film 3 of a different material isdeposited so as to cover the sacrificial layers 30. The material of theinsulating film 3 selected is a material with a high selectivity withrespect to the sacrificial layers 30. For example, the sacrificiallayers 30 are made silicon nitride films, while the insulating film 3 ismade a silicon dioxide film. Further, parts of the insulating film 3remain in the end as the sidewalls, so the material and method offormation are selected in consideration of the quality and insulationcharacteristics etc. of the film.

Next, the insulating film 3 is etched back by anistropic etching. Due tothis, as shown in FIG. 44A and FIG. 44B, sidewalls SW are formed at thesides of the sacrificial layers 30. The widths of the sidewalls SW aremainly determined by the height of the sacrificial layers 30 and theconditions of the anistropic etching. When the anistropy is strong to acertain extent, however, even if the etching time varies somewhat, thewidths of the sidewalls do not change much, so the uniformity isrelatively high.

Next, the sacrificial layers 30 are selectively removed by apredetermined method. For example, with removal in the case where thesacrificial layers 30 are silicon nitride, wet processing using anetching including phosphoric acid (H₃PO₄) is performed. Due to this,sidewalls SW remain as shown in FIG. 45A and FIG. 45B.

As shown in FIG. 46, a conductive film 4 completely burying thesidewalls SW, for example, a film of a metal, doped polycrystallinesilicon, or doped amorphous silicon, is deposited.

Next, for example, CMP or another method is used to grind and/or polishthe surface of the conductive film 4. The grinding and/or polishing iscontinued until the sidewalls SW are exposed, the conductive film 4isolated into a plurality of regions, and the isolation distance becomesthe necessary value. Due to this, as shown in FIG. 47A and FIG. 47B, aplurality of word lines WL1, WL2, . . . WLn and control gates SG1 andSG2 isolated by the sidewalls SW are formed at the necessary distances.

Note that the grinding and/or polishing is continued until the chargetrap film CHS is completely separated for each word line. In the case ofan FG type where the charge storage film is a conductive material,however, separation of the charge storage film becomes essential. Thisis because if a floating gate FG is connected at such a location, thestored charge would leak to the adjoining cell and therefore datastorage itself would become impossible. Further, sufficient grindingand/or polishing is necessary to avoid concentration of the electricfield at that portion.

As shown in FIG. 48, the control gate lines SG1 and SG2 are made tobecome predetermined line widths by forming a mask layer covering partsof the word lines WL1, WL2, . . . , WLn and the control gate lines SG1and SG2 and etching it to selectively remove the peripheral portions ofthe mask layer.

The mask layer is removed, then an N-type impurity is injected into thesemiconductor substrate SUB. At this time, the ion injection conditionsare determined so that the ions will not pass through the interconnectline layer portions, but the ions will pass through the sidewallportions to reach the substrate. Due to this, the source-drain regionsS/D, drain regions DR, and common source lines CSL are simultaneouslyformed. At this time, the preformed element isolation layer may alsofunction as a mask at the time of ion injection.

Note that when it is difficult to form source-drain regions S/D havingthe desired concentration and depth by just optimization of the ioninjection conditions, the sidewalls SW may be removed once, the ionsinjected, then the sidewall shaped spaces buried with an insulatingmaterial again.

Next, the interlayer insulating film INT is deposited, the bit contactsBC are formed, and the bit lines are formed to complete the nonvolatilememory.

10TH EMBODIMENT

The 10th embodiment shows a first modification of the formation of wordlines of a nonvolatile memory.

FIG. 50A to FIG. 50C and FIG. 51A to FIG. 51D are sectional views alongthe line width direction shown centered on the word line portion. Thisembodiment can also be applied to any of the types of memory cell arraysof the eighth and ninth embodiments.

In the interconnect line isolation structure in the 10th embodiment, asshown in FIG. 51D, in addition to the sidewalls SW, the interposition ofa thin thermal oxide film 10 between the charge storage film GD at thefirst shape word line WL2, WL4, . . . side and sidewalls SW differs fromthe eighth and ninth embodiments.

The thermal oxide film 10 is obtained by thermal oxidation of dopedpolycrystalline silicon or doped amorphous silicon. Therefore, thecontrollability of the film thickness is extremely high. Further, sincethe film is silicon dioxide obtained by thermal oxidation, it is good inquality. Therefore, there is the advantage that the insulationcharacteristics between interconnect lines are improved.

In the formation of the interconnect line structure, first, as shown inFIG. 50A, the substrate SUB is formed with a sacrificial layer 40 at apitch of about two times the final interconnect lines. This sacrificiallayer 40 is formed from doped polycrystalline silicon or doped amorphoussilicon.

As shown in FIG. 50B, the surface of the sacrificial layer 40 isthermally oxidized to form a thermal oxide film 10 comprised of severalnm to several tens of nm of silicon dioxide. Note that instead ofthermal oxidation, it is also possible to nitride or oxynitride thesurface by heating.

Next, in the same way as in the eighth and ninth embodiments, aninsulating film 3 is deposited (FIG. 50C) and etched to form sidewallsSW (FIG. 51A).

Further, the top surface of the sacrificial layer 40 is exposed, thenthe sacrificial layer 40 is selectively removed (FIG. 51B), a conductivefilm 4 is deposited (FIG. 51C), and this is ground and/or polished toform a plurality of word lines WL1 to WL5 (FIG. 51D).

In the 10th embodiment, it is possible to effectively improve theinsulation characteristics of the dielectric between the word lines justby thermal oxidation or other processing. Note that since thesacrificial layer 40 is comprised of a conductive material unlike thesidewalls etc., there is the advantage that selective etching is easy.

11TH EMBODIMENT

The 11th embodiment shows a second modification of the formation of wordlines of a nonvolatile memory.

FIG. 52A to FIG. 52C and FIG. 53A to FIG. 53C are sectional views alongthe line width direction centered on the word line portion. Thisembodiment may also be applied to any type of memory cell array of theeighth and ninth embodiments.

In the interconnect line isolation structure of the 11th embodiment, asshown in FIG. 53C, as multilayer films having a charge storage capacity,there are the first charge storage film GD1 between the first shape wordlines WL2, WL4, . . . and substrate SUB and between the sidewalls SW andsubstrate SUB and the second charge storage film GD1 between the secondshape word lines WL1, WL3, . . . and substrate SUB. Further, a thinthermal oxide film 10 is interposed between the first shape word linesWL2, WL4, . . . and the sidewalls SW. This embodiment differs from theeighth and ninth embodiments in these points.

The first charge storage film GD1 and second charge storage film GD2 arethe same in specifications of the film structures.

The thermal oxide film 10 is obtained by thermal oxidation of thesurfaces of the first shape word lines WL2, WL4, . . . when they arecomprised of doped polycrystalline silicon or doped amorphous silicon.Therefore, the controllability of the film thickness is extremely high.Further, since the film is silicon dioxide obtained by thermaloxidation, it is good in quality. Therefore, there is the advantage thatthe insulation characteristics between interconnect lines are improved.

In the formation of this interconnect line structure, first, as shown inFIG. 52A, the substrate SUB is formed with a first charge storage filmGD1, then formed with first shape word lines WL2, WL4 . . . at a pitchabout twice the final pitch. The first shape word lines WL2, WL4, . . .are formed from doped polycrystalline silicon or doped amorphoussilicon.

As shown in FIG. 52B, the surfaces of the first shape word lines WL2,WL4, . . . are thermally oxidized to form the thermal oxide film 10comprised of several nm to several tens of nm or so of silicon dioxide.Note that instead of thermal oxidation, nitridation or oxynitridation byheating are also possible.

Next, in the same way as the eighth and ninth embodiments, theinsulating film 3 is deposited (FIG. 52C) and etched to form thesidewalls SW (FIG. 53A).

Here, in the 11th embodiment, as shown in FIG. 53A, the first shape wordlines WL2, WL4, . . . and sidewalls SW are used as a mask to remove thesurrounding first charge storage film GD1.

Next, the second charge storage film GD2 is formed over the entiresurface, then the conductive film 4 is deposited (FIG. 53B) and this isground and/or polished to form the plurality of word lines WL1 to WL5(FIG. 53C).

In the 11th embodiment, it is possible to effectively improve theinsulation characteristics of the dielectric between the word lines byjust thermal oxidation or other processing. Further, steps for partialremoval and reformation of the charge storage film are added, but thefirst shape word lines are not removed, so the number of steps does notchange much.

Summarizing the effects of the present invention, it is possible togreatly reduce the distance between word lines and other interconnectlines of for example semiconductor memory devices to less than the limitof photolithography and as a result slash waste of space. In particular,when applying this interconnect line isolation structure to isolation ofword lines of a memory cell array, it is possible to greatly reduce thedimensions of the memory cells in the column direction and greatlyreduce the bit cost by that extent.

Further, it is possible to takeout electrodes though the pitch of wordlines is small.

Further, with the method of producing a semiconductor device accordingto the present invention, the above interconnect line isolationstructure can be easily formed without using any special process and byusing ordinary photolithography and etching techniques.

The distance between interconnect lines is defined by the thickness ofthe insulating film and/or the width of the sidewall insulating layer.

The insulating film can be controlled to an extremely high precision asis well known.

Further, the width of the sidewall insulating layer can be controlled bythe height of the sacrificial layer or first shape interconnect linesand the etching conditions of the dielectric. The etching at the time offormation of the sidewall insulating layer is normally performed understrongly anistropic conditions, so even if the etching time fluctuatessomewhat, there is little variation in the width of the sidewalls.Therefore, the uniformity of the width of the sidewall insulating layeris comparatively high. Further, when an insulating film is interposed inaddition to the sidewall insulating layer, the width is determined bythe film thickness, so is extremely uniform.

Due to this, the fluctuation in distance between interconnect lines isconsiderably small.

Further, with the method of production according to the presentinvention, it is possible to keep down to a minimum the introduction ofsubstrate damage and etching of the first word lines.

Due to the introduction of etching of the substrate surface, fluctuationin thickness of the charge storage film due to formation of the firstword lines and second word lines in two steps is effectively suppressedand fluctuations in characteristics are prevented.

Further, since there is a step of electrical isolation (removal ofresidue) of the second word lines, it is possible to keep over etchingto the minimum necessary and maintain the insulation and isolationcharacteristics between the word lines at a high level when forming thesecond word lines. Further, it is possible to suppress or preventleakage current at the time of reading data.

While the invention has been described with reference to specificembodiments chosen for purpose of illustration, it should be apparentthat numerous modifications could be made thereto by those skilled inthe art without departing from the basic concept and scope of theinvention.

The present disclosure relates to subject matter contained in JapanesePatent Application No. 2002-007085, filed on 16 Jan. 2001, thedisclosure of which is expressly incorporated herein by reference in itsentirety.

1. A semiconductor device comprising: a plurality of memory transistorsarranged in an array; a plurality of word lines extending in a rowdirection and repeating at distances in a column direction, said wordlines being gate electrodes for said plurality of memory transistors; afirst charge storage film on a semiconductor, said first charge storagefilm including a plurality of first films and having a first chargestorage capability; first word lines of said plurality of word lines onsaid first charge storage film and in parallel with each other atpredetermined distances; a second charge storage film covering surfacesof said first word lines and surfaces of said semiconductor exposedbetween said first word lines, said second charge storage film includinga plurality of second films and having a second charge storagecapability; second word lines of said plurality of word lines facingsaid surfaces of said semiconductor exposed between said first wordlines across said second charge storage film, said second word linesbeing insulated and isolated from said first word lines by said secondcharge storage film; a first word line drive circuit connected to atleast one of the outermost second word lines and supplying apredetermined voltage for turning off a channel at all times regardlessof an amount of stored charge in said second charge storage filmdirectly under said second word line or injecting a sufficient amount ofcharge to said second charge storage film by supplying a voltage forturning off the channel at all times; and a second word line drivecircuit connected to said first or second word lines and controlling,based on an input row address signal, a voltage suitable for input andoutput of a charge to a first or second charge storage film directlyunder said first or second word lines or a voltage suitable for turningon or off a channel in accordance with the amount of stored charge insaid first or second charge storage film, wherein the number of saidsecond word lines is one larger than the number of said first wordlines, wherein said first word lines and said second word lines extendoutward from a memory cell array region and then are bent in a directiondifferent from a direction of arrangement of said word lines, andwherein a pitch of arrangement between said first word lines and saidsecond word lines at front end sides from said bent portions is setlarger than a pitch of arrangement between said first word lines andsaid second word lines in said memory cell array.